The present invention relates to integrated circuits having circuit elements subject to increased transmission delay with age and in particular to a method and apparatus for anticipating age-related failure of the gates of an integrated circuit.
Logical gates are building block circuit elements of digital integrated circuits that implement a Boolean function using multiple transistors to receive an input at one or more inputs, interpret the inputs as logic levels, and provide an output voltage being the Boolean function of the inputs. Logical gates generally form building components of more complex devices including counters, storage registers, and the like.
Future generations of integrated circuits such as microprocessors are increasingly likely to fail in the field because of device faults at logical gates. The failure may be a “soft failure” where the logical gate operates, but at a reduced level of performance that prevents it from coordinating with other components of the integrated circuit (for example, an increased gate delay which prevents successful propagation of high-speed signals) or “hard failure” where the logical gate ceases to perform any useful function.
A number of age-related wearout mechanisms for logical gates have been identified. Bias temperature instability (BTI) may occur when a negative bias is applied to a gate at elevated temperature causing holes/electron pairs to migrate to the silicon-oxide interface. This increases the threshold voltage of the gate increasing a gate delay. A 10 percent to 15 percent degradation in threshold voltage can cause a delay degradation of 15 percent over three years of continuous operation.
Hot carrier injection (HCl) occurs occasionally when carriers (elections or holes) gain sufficient kinetic energy to break into the gate dielectric. Over time this accumulation of carriers in the dielectric causes degradation (increase) in the threshold voltage.
Time-dependent dielectric breakdown (TDDB) can occur when longtime application of the low electrical fields causes gate oxide degradation. Eventually this degradation may lead to the formation of a conductive path from the gate to the substrate irreversibly damaging the gate.
The failure of an integrated circuit caused by logical gate failure may be detected by comparing the operation of redundant integrated circuit modules under the assumption that both will not fail simultaneously in the same way. This approach incurs significant power overhead and design complexity from the need to create and simultaneously operate redundant components.
The power overhead of operating two redundant components in parallel can be reduced by a sampling approach in which the comparison process is implemented only after specified or random intervals of time. This sampling approach, however, can miss faults that result in errors that occur infrequently.
The problem of failing to detect infrequent faults can be minimized through fault prediction that allows a response before actual faults occur. Two principal techniques of fault prediction are “canary-based” and “in-situ” faults which both attempt to predict faults by detecting the early signs of aging in increasing gate delays.
Canary-based fault prediction provides a special test circuit using gates that are in the same environment and have the same device technology as gates in the broader integrated circuit but which can be more easily monitored for increased gate delay. Canary-based fault prediction suffers from the difficulty of exactly matching the “canary circuit” to the target circuit, termed the “accuracy” problem.
“In-situ” fault prediction monitors actual gates of the target circuit eliminating the accuracy problem. Nevertheless, in situ fault prediction is practically limited to a small subset of those gates and thus suffers from poor generality, missing possibly significant increases in gate delays in gates that are not monitored.